1. Technological Field
The present disclosure relates to a three-dimensional resistive memory array and a method for forming the same.
2. Description of the Related Technology
There is a continuous need for increasing bit density and reducing bit cost in memory devices, and new alternatives are being proposed for ultra-high density memory technologies, such as, three-dimensional stacked resistive random-access memory (3D RRAM) devices.
One possibility for advanced scaling of RRAM device in 3D consists of vertically stacking of horizontal planes, the horizontal planes each comprising a memory array with 1 selector and 1 RRAM cell. This is however a more pseudo-3D approach for which the manufacturing process is too costly. Another possibility is the so-called 3D RRAM BICS approach as for example disclosed in U.S. Pat. No. 8,063,438. A vertical-type RRAM device is disclosed including an insulation layer pattern of a linear shape provided on a substrate and pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided, also in the vertical direction, on a sidewall of each of the single-crystalline semiconductor patterns.
There is a need for alternative solutions to manufacture 3D RRAM devices which comprise a resistor and a selector, preferably a transistor (1T1R) in the cell.